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Espressif Systems /ESP32-C3 /SPI2 /SLAVE

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Interpret as SLAVE

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CLK_MODE 0 (CLK_MODE_13)CLK_MODE_13 0 (RSCK_DATA_OUT)RSCK_DATA_OUT 0 (SLV_RDDMA_BITLEN_EN)SLV_RDDMA_BITLEN_EN 0 (SLV_WRDMA_BITLEN_EN)SLV_WRDMA_BITLEN_EN 0 (SLV_RDBUF_BITLEN_EN)SLV_RDBUF_BITLEN_EN 0 (SLV_WRBUF_BITLEN_EN)SLV_WRBUF_BITLEN_EN 0DMA_SEG_MAGIC_VALUE 0 (MODE)MODE 0 (SOFT_RESET)SOFT_RESET 0 (USR_CONF)USR_CONF

Description

SPI slave control register

Fields

CLK_MODE

SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.
CLK_MODE_13

{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].
RSCK_DATA_OUT

It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge
SLV_RDDMA_BITLEN_EN

1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others
SLV_WRDMA_BITLEN_EN

1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others
SLV_RDBUF_BITLEN_EN

1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others
SLV_WRBUF_BITLEN_EN

1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others
DMA_SEG_MAGIC_VALUE

The magic value of BM table in master DMA seg-trans.
MODE

Set SPI work mode. 1: slave mode 0: master mode.
SOFT_RESET

Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state.
USR_CONF

1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data